Polysilicon transistors have been widely used, especially as active load devices in static random access memory (SRAM) cells. Examples of the use of polysilicon transistors may be found in (i) "Polysilicon Transistors in VLSI MOS Memories," by H. Shichijo, et al., IEDM pp.228-31, 1984; (ii) "A 25 UM2 New Poly-Si PMOS Load (PPL) SRAM Cell having Excellent Soft Error Immunity," by T. Yamanaka et al. IEDM, pp.48-51, 1984; and (iii) "a 0.1-uA Standby Current, Ground-Bounce-Immune 1-Mbit CMOS SRAM," by M. Ando et al., IEEE Journal of Solid-State Circuits, Vol. 24, No. 6, December 1989, pp. 1708-13. Each of the above articles is hereby incorporated by reference in its entirety.
FIG. 1 shows a six-transistor CMOS SRAM cell (6-T cell) suitable to be used in a memory array accessible by a two-part address selecting a word line WL and a bit line BL. The transistors in the 6-T cell include two PMOS pull-up transistors (the active load transistors) 102a and 104a, two NMOS transfer transistors 100 and 105, and two NMOS pull-down transistors 101 and 103. The transfer transistors 100 and 105 are controlled by the word line WL, which, when selected, enables a data bit to be read from or written into the 6-T cell on the complementary bit lines BL and BL.
FIG. 2 shows a four-transistor SRAM cell (4-T cell) suitable for use in a memory array similar to that discussed above for the CMOS 6-T cell shown in FIG. 1. This 4-T cell differs from the CMOS 6-T cell discussed above by having load resistors 102b and 104b in place of the active load transistors 102a and 104a, respectively. The load resistors 102b and 104b are typically resistors made up of high-resistivity polysilicon. One advantage the 4-T cell has over the 6-T cell is its smaller size resulting from having two less transistors. Unlike active load transistors, which are high impedance in the "off" state, and low impedance in the "on" state, load resistors must be designed within a range of values in which the switching speed of the memory cell must be traded-off against the attendant load and leakage currents. Leakage currents in a 4-T cell are always larger than leakage currents in a 6-T cell. In recent years, the requirement of high resistivity in the polysilicon making up the load resistors has led to lower yield, because the higher density in memory chips results in smaller margins between load and leakage currents. Because the 6-T cell has more preferable electrical characteristics, and is easier to manufacture, the 6-T cell design is generally more preferable.
The ability to build three dimensional structures involving multiple layers of polysilicon allows polysilicon transistors, which may be stacked on top of single-crystalline CMOS transistors, to be used as load transistors in a six-transistor SRAM cell. These polysilicon transistors have similar desirable impedance characteristics in their on and off states as the single-crystalline silicon PMOS transistors. T. Yamanaka et al., incorporated by reference in the above, showed a stacked structure including a polysilicon transistor on top of an NMOS transistor, using a triple-polysilicon process. Because of the three-dimensional nature of this structure, the latch-up rules required in a CMOS implementation of the 6-T cell are eliminated, resulting in a smaller implementation than the CMOS counterpart for the same feature size. Schematically, such a 6-T cell will be identical to that shown in FIG. 1, with the understanding that transistors 102a and 104a are polysilicon PMOS transistors, rather than single-crystalline silicon transistors.
FIG. 3 shows an idealized polysilicon PMOS transistor 20. The source 200, drain 202, and channel 201 regions are formed from the same mask level of polysilicon. The source 200 and drain 202 are heavily doped p-type polysilicon and the channel region 201 is preferably lightly doped p-type polysilicon. The gate 203 is formed on another mask level of polysilicon separated by an insulating oxide layer 204.
Since density is an overriding concern in memory designs, it is highly desirable to be able to minimize the cell area.